Intel Vs. TSMC: Process Technology Leadership Is More Than Transistor Density (NASDAQ:INTC)

Investment Thesis

Much of TSMC’s (NYSE:TSM) growth comes from advanced process technology nodes, which serve to follow Moore’s Law: they deliver up to a 2x improvement in transistor density per generation, every two to three years. This provides chip designers with a larger transistor budget, of more powerful and more efficient transistors, which allows them to increase functionality. Furthermore, cost per transistor also tends to come down.

For Intel (INTC), likewise, reaping the benefits of Moore’s Law has been and continues to be vital for being able to compete with its product offerings and expand to new markets such as IoT, GPUs, and AI.

Given that Moore’s Law is an exponential trend, even being ahead by just one step could deliver a tremendous competitive advantage. For example, for gamers, a 2x better GPU could mean achieving 60fps instead of 30fps.

In a past article, I explored the future of Intel vs. TSMC. I noted that Intel had lost its lead, which it had previously firmly established with its Tick-Tock cadence, due to its 3-year 10nm delays. However, those delays were now behind, and Intel seemed to have restored its 2-year cadence goal. Meanwhile, TMSC’s 3nm node promised just a 1.7x improvement (tangibly lower than 2x) despite being on a more moderate 2.5-year cadence. This would give Intel time to catch up and go back to parity, in density, in the next several years.

At least, in theory. Since writing this article, Intel announced its 7nm delay. I have made some adjustments were necessary.

Nevertheless, as the title of the present article suggests (and what this article is about), there is more to semiconductor process technology than just the transistor density metric that investors and even tech enthusiasts mainly focus on. And, in those aspects, TSMC’s well-known and established process leadership isn’t as clear. (Indeed, while the 7nm delays were announced, Intel also announced 10nm SuperFin.)

This article should put some nuance to the common view nowadays that TSMC has a tangible lead.

For investors, while TSMC and Intel are only indirect competitors at best, process technology is, of course, one of the key discussion points related to both companies, so being aware of how these companies stack up could improve investment decisions.


For illustrative purposes, following is a recent quote by Nvidia‘s (NVDA) CEO, one of Intel’s prime competitors:

Jensen Huang

“Process technology is a lot more complex than a number. I think people have simplified it down to an almost a ridiculous level”

Performance and Power

The argument of this article is that performance and power of transistors are just as important (as density). Nanometer numbers are already just marketing (see Intel: The Nanometer Games (NASDAQ:INTC)), instead of referring to actual transistor sizes, and say even less about how much energy a transistor consumes when switching, or how fast it can switch.

First and foremost, though, when it comes to such other metrics besides density, admittedly, they are somewhat less clear than a simple number such as transistors per area (for density). They are (also) influenced greatly by top-level design decisions. (Although the same also holds for density, it can be measured much more easily.)

Transistor Innovations

I will illustrate this aspect of transistors by running down some historical examples:

  • In the late 1990s, transistor performance scaling (known as Dennard scaling) was reaching a limit and preluded the end of the GHz wars. Intel invented a technique known as strained silicon at 90nm in 2001, before others followed at 65nm around 2004. Further enhancements of this technique have allowed transistors to continue to improve in drive current (performance) over time.
  • Further, not all transistors’ features have the same length. For example, there is a relatively small insulating layer between the gate (which controls the transistor) and the source-drain (where current flows). In the early 2000s, this layer was approaching a small width measured in monolayers of atoms. Not being able to scale this further would further contribute to lower performance gains. Its small width also resulted in vast increase in leakage (due to quantum effects). To overcome these issues, Intel introduced a set of materials science innovations known as HKMG (high-k, metal gate) in 2007 at 45nm, before others copied this at 28nm around 2011-2012. These have mitigated leakage increasing to unsustainable levels, as well as allow continued feature size scaling (hence, prevent Moore’s Law from ending).
  • Nevertheless, the historical CMOS transistor as it was known was still seen running out of steam (despite HKMG), as leakage kept being an issue. Being able to shrink features is one thing, indeed, if you can’t also reduce power and ever-increasing leakage as you make things smaller (especially relevant in the mobile era of last decade). Intel, again, led the way with developing Tri-Gate/FinFET. This was a new transistor ‘architecture’, so to speak, which allows the gate to wrap more fully around the source-drain channel. Hence, this increases current control, or in other words, reduces leakage. Intel introduced this at 22nm in early 2012, before others at 16nm in early 2015.
  • Of note, while FinFETs provided a step-size reduction in power, this did not help Intel succeed anyway after being late to enter the smartphone market. This was, of course, more because of market dynamics than because of technology. So, unfortunately, for Intel, since it missed the mobile revolution (because this was an evolution from phones to smartphones rather than a miniaturization of the PC like laptops), it failed to capitalize on its multi-year FinFET advantage where it would have been an especially significant advantage.
  • Also, of note, TSMC’s 20nm remained planar. But, tellingly, it is one of TSMC’s least successful nodes ever. The best example of this is GPUs: Nvidia and AMD (NASDAQ:AMD) both skipped 20nm, despite 20nm offering a 1.9x increase in density. It turns out more transistors aren’t very useful if there is no power budget to feed those.
  • Also, of note, TSMC was likely caught off guard by Intel’s industry-leading introduction of FinFETs at 22nm. As explained in my Nanometer Games article, TSMC pulled-in its FinFET from its 14nm node, inserted it in its 20nm process, and called this “new” process 16nm (and hence renamed its 14nm to 10nm, 10nm to 7nm, etc.).
  • In the FinFET era, performance of FinFETs can be further increased by increasing the height of the fin, or using more fins at the expense of transistor density.
  • The reverse is called fin depopulation: using less fins per transistor. This has been possible and has happened over the generations as FinFETs increased in performance. In this way, performance improvements are actually responsible for density improvements, curiously enough.

Each of the three major materials science innovations noted above (strained silicon, HKMG, FinFET) provided Intel with a great process technology advantage, as Intel introduced them three to four years ahead of other leading edge foundries. (It was, of course, cutting edge technology innovations like these, bare none, that drew me to Intel.)

Yet, they are only loosely related to density: they were invented to continue historic scaling, but they have also provided benefits in power and performance beyond just scaling.

Interconnect Innovations

Furthermore, there is not just the transistor. Just as importantly, there is also the interconnect, which as the name implies connects transistors. By analogy: its function is that transistors would act more like a domino chain rather than individual (useless) pieces.

The interconnect stack, known as back-end of line (BEOL) consists of >10 metal layers nowadays. Several further trends can be noted here:

  • The interconnect is also a bottleneck for power and performance: individual transistors can actually switch at up to tens or hundreds of GHz. It is also increasingly a bottleneck for scaling.
  • At 14nm, Intel introduced ‘air gaps’ between a few select layers. Air, as some readers may be aware of, is one of the best insulators, so this indeed improved power and performance. Intel is still the only fab with air gaps. So, in that aspect, Intel currently has a six-year lead, and counting.
  • The lowest layers, most closely to the transistor, are also referred to as the middle-of-line (MOL). Here, Intel introduced cobalt (Co) at 10nm along with Ruthenium, but also used Cobalt in the lowest layers of the interconnect stack, bringing significant improvements.
  • While TSMC also introduced Cobalt at 7nm, this wasn’t in the interconnect, but only the MOL.
  • To continue transistor scaling, before EUV, the industry used multiple patterning: exposing the wafer multiple times instead of just once. Intel to date remains the only fab to have used quadruple patterning in the interconnect layers, although Intel said this was one of the reasons for its yield problems.
  • Intel’s 10nm SuperFin’s industry-first Super MIM brings a 5x increase in capacitance (at the same area) compared to the rest of industry. Clearly, this is a significant process innovation.
  • Intel’s chief engineer Murthy has said that the interconnect also will be important at 5nm.

More in general, all innovations noted above (except FinFET perhaps) could be referred to as materials science innovations. From the introduction dates, I noted (and even continuing through 10nm SuperFin), it should be clear that Intel’s historical materials science innovation lead and innovation are unparalleled bar none.

(Note: it isn’t yet clear to what extent Intel’s 2023 production goal for 5nm is impacted by the 7nm delays.)


As transistors and feature sizes between transistors continue to become smaller, semiconductor innovations will still be needed as in the last two decades.

  • The FinFET can be further improved upon by wrapping the gate fully around the channel. In the near future, the industry will indeed move beyond the FinFET (tri-gate), to gate-all-around (“four-gate”) or GAA in short.
  • This will provide similar benefits as the move to FinFETs, although the theoretical benefit is not as large as planar to FinFET.
  • Intel will do this at its 5nm (late 2023, according to Murthy), Samsung (OTC:SSNLF) at 3nm in 2022 and TSMC at 2N in 2024/2025.
  • Power and performance of FinFETs and nanowires can be further increased by changing the channel material from silicon to Ge or a III-V combination.
  • Nanowires can be oriented horizontally or vertically.
  • It is unclear what the industry will do when nanowires run out of steam, but the range of options (in research) is large.
  • Besides moving to GAA, another future improvement could be changing the channel material (where current flows) to a post-silicon material.
  • Beyond GAA, there are literally dozens of future post-CMOS options in various stages of research. Spintronics, carbon nanotubes, quantum tunneling… In its research, Intel seems to favor spintronics, TSMC carbon nanotubes, although nothing is yet really moving to development.
  • Intel in 2018-2019 announced a highly futuristic possible post-CMOS quantum device it is researching, called MESO.

Intel possibly moving to gate-all-around (GAA) aka nanowires at 5nm ahead of TSMC 2N strongly indicates that Intel could still continue to lead in this materials science and transistor innovation aspect of Moore’s Law, even if it is somewhat behind in density.

It also shows the “nanometer games” as I called it, as Intel’s 5nm could be just as advanced as TSMC’s 2N, despite the seemingly vast difference in name. (For comparison, a silicon atom is about 0.2nm.)

Sub-threshold Slope

As a slightly more technical section (if the others aren’t already, but feel free to skip), to illustrate one metric (transistor specification) other than transistor density, there is a key transistor metric known as the sub-threshold slope.

Transistors themselves aren’t as binary as computer programmers are used to. In general, drive current increases as a voltage is applied to the gate. Moreover, as the term leakage implies, even a transistor in the ‘off’ state can still have some current flowing.

Being ‘on’ or ‘off’ requires a difference in drive current of several orders of magnitude in most chips. Given there is only a finite increase in drive current as voltage is increased, this means there is some minimum voltage required for a transistor to be considered ‘on’, called the threshold voltage.

Therefore, the (exponential) rate at which current increases (when increasing the voltage) determines this threshold voltage. Therefore, technologies that can improve this metric could allow for a substantial reduction in operating voltage. And since power/energy scales quadratic in function of voltage, this could lead to serious improvements in the power consumption and energy efficiency of chips (although perhaps at the cost of peak performance).

This is called the sub-threshold (drive current) slope. It is measured in mV/decade: how many millivolts it takes to increase drive current by 10x. Lower is better.

For silicon/CMOS, the theoretical limit is 60mV/dec. Planar transistors achieved down to low triple-digit values (~100-120).

FinFETs, in fact, have been able to lower this down to quite close to the limit, at around ~65mV/dec. This further shows the advantage Intel had with its three-year FinFET lead. (If only Intel’s leadership/management had foreseen the importance of smartphones, or the usefulness of this for GPUs, etc.)

In any case, this limit shows that beyond-CMOS technologies could further provide substantial improvements, at least with regards to power/energy consumption: other technologies could have steeper sub-threshold slopes than CMOS’ 60mV/dec. Perhaps as low as ~20mV/dec or even less.

Real-world Implications

I will now summarize some of the real-world product benefits these innovations have brought:

  • Intel’s Core CPUs on 45nm (the HKMG node) helped it widen the gap with AMD and take back market share and definite CPU leadership (for the next >1 decade).
  • Intel’s planar transistor CPUs achieved around ~4.6GHz with 32nm Sandy Bridge. Given that FinFETs mostly reduced power with less focus on performance (initially), its 22nm successors Ivy Bridge regressed in clock speed.
  • However, improved FinFETs (taller, more rectangular), air gaps and perhaps others techniques have allowed 14nm Skylake to eventually beat planar transistors in performance, and 14nm++ today achieves up to 5.3GHz (single core) in commercial products.
  • Ice Lake (10nm) reached 3.9GHz in its 15W configuration, 4.1GHz at 28W. Tiger Lake (10nm SuperFin) is set to improve this to ~4.8GHz. This shows that process enhancements can continue after process introduction and result in significant improvements (even if in this case just to go back to parity with the previous generation).
  • AMD’s Zen hardly surpassed 4.0GHz. 7nm-based Zen 2 has improved this, but still readily trails 14nm++ in frequency.
  • As noted above, Nvidia and AMD both skipped 20nm because it lacked FinFET (and an HP-focused design library). Also, 20nm didn’t improve cost per transistor. Just like with power, you can’t really implement more transistors – make use of Moore’s Law – if the cost per transistor doesn’t decline.
  • Qualcomm’s Snapdragon 600 at the time (if I remember correctly) was a meaningful improvement over the Snapdragon S4, despite being the same architecture, but it was upgraded from 28nm to TSMC’s 28nm version with HKMG (which TSMC had so diligently copied from Intel four years after Intel).
  • Intel’s 22FFL process, announced in 2017 as a low-cost FinFET process, features an ultra-low leakage transistor with 100x lower leakage. TSMC simply has no equivalent/competition for this at all, as its own competing process uses a planar transistor. Or had no equivalent, as TSMC recently announced such a 12nm variant. This means TSMC, seen as the world’s leading foundry, is lagging behind Intel by 3-4 years in introducing a mainstream FinFET node.
  • While again also (or even: mostly) a function of product design, Apple (NASDAQ:AAPL) has yet to reach 3GHz frequency for its CPU cores. So, even if Apple has a somewhat better architecture, Intel CPUs will speed right past this towards 5GHz. This is especially relevant, given Apple’s upcoming transition towards ARM-based Macs.
  • Lastly, people ever continue to compare power consumption of phone chips to laptop chips, or even continue to fall into the ARM vs. x86 (RISC vs. CISC) fallacy that was debunked many years ago with Intel’s short venture into phone chips (the FinFET advantage described above). But also a more modern example such as Intel’s Lakefield continues to demonstrate that its x86 chips (both Core and Atom) have no difficulty to be used in low-power designs.

Given the 7nm delays, Intel may even further develop improvements of its 10nm technology as it will now have to use this longer than planned (unless it goes to TSMC). Intel argued this would allow it to deliver another step of Moore’s Law improvements (aside density) within 10nm, which 10nm SuperFin already demonstrates. To that end, perhaps some of the materials science innovations slated for 7nm(+)(+) could be introduced in the upcoming 10nm++(+).

By definition, such intra-node improvements depend mostly on materials science innovation (for power/performance) rather than density improvements.


Transistor technology is far more than feature sizes and density numbers. Intel since the early 2000s has had a historical and significant 3-year lead in leading edge materials science innovations, with the important trifecta of strained silicon, HKMG and FinFET proving this. Further innovations include air gaps and Cobalt in the interconnect (which TSMC does not have). While not directly impacting transistor density, this is also process technology, and hence should be taken into account when comparing and discussing process leadership.

Obviously, but admittedly, if Intel had a 3-year lead in such innovations (as it did), but 10nm has been delayed by 3 years, then also, this lead can be questioned, going forward. Indeed: Samsung will move to gate-all-around ahead of Intel.

Nevertheless, such a pipeline of research and innovation does not just disappear because one node has yield issues.

Intel’s introduction of + and ++ intra-node variants with meaningful enhancements shows this. For instance, it has been said that 14nm+/14nm++ took features from 10nm. This might be one way that, for example, a 10nm+(+) or 7nm(+)(+) in the future might reduce the impact of this 3-year delay, if likewise they respectively implement features from 7nm/5nm, perhaps, and continue to show the power-performance aspect of process technology as described in this article.

Indeed, given the characteristics of 10nm SuperFin as announced, this likely could compete against TSMC’s 5nm in those aspects, closing the gap in power and performance.

Or conversely, Intel might improve its execution by spreading out innovations in the + and ++ nodes, reducing the risk of combining too many features in one node.

So, summed up, power and performance (and cost per transistor) are just as critical to products and to advance Moore’s Law. You can’t use more transistors if you have no power, or cost, budget for them. For performance, especially relevant in CPUs (where most of Intel’s revenue comes from) TSMC, by no means has any performance lead that it could reasonably claim to possess (as opposed to its ~1-year transistor density lead), as the clock frequencies of Intel’s 14nm++(+++++) CPUs prove, although at the cost of a power consumption disadvantage, but 10nm (Enhanced) SuperFin will also improve this.

As discussed, all these aspects beyond density also are heavily influenced by materials and transistor science innovations.


There is much more to a process than just its density. Not all products even need the highest density in the first place. While it’s true that, in general, new nodes come with a package of benefits that includes, besides density, also lower cost, lower power as well as higher performance, some critical innovations such as HKMG and FinFET have resulted in step-size (above average) improvements in some aspects, such as leakage, even if this isn’t as easily quantifiable or predictable as density.

Historically, and even at 10nm, Intel has had a (time to market) lead in many such important innovations. A leadership in those aspects may mitigate a shortfall in density. Indeed, as I claimed in my unpublished 10nm SuperFin article, this node instead might perhaps be seen as the most cutting edge (“process leadership”) node currently in production.

Implications for TSMC

Most notorious is TSMC’s short-lived 20N node because it lacked the FinFET architecture. Similarly, 3N lacks its successor, gate-all-around (while the competition is charging ahead with those), so this may or may not warrant some preliminary cautiousness about this node.

Implications for Intel

For Intel investors, the 14nm+ and 14nm++ intra-nodes should provide at least some assurance that Intel’s highly successful materials science pipeline and leadership didn’t just disappear together with the 10nm delays. In the case of 10nm, 10nmSF and 10nmESF will be helping Intel to recover somewhat. The 10nmSF of the upcoming Tiger Lake should allow Intel to compete much more readily than Ice Lake’s 10nm, as it allows for much higher frequencies. Intel has said it is waiting for 10nmESF to introduce 10nm on the desktop, also for frequency-related reasons.

In the future, while Intel won’t be the first to transition to GAA (as Samsung will be), it will still be ahead of TSMC (at the last confirmed roadmap schedules), and Intel’s historical materials science knowhow may make them able to deliver a much better implementation of this technology. For example, with GAA, one could stack multiple wires on top of each other, providing a vast density increase without having to shrink the transistor. Perhaps, that could allow Intel to regain a density lead in the future. Or perhaps, Intel has some other technologies in the pipeline that it will introduce years before Samsung and TSMC, but that is speculation (although Intel made some noise about the MESO device it has invented).

So, admittedly, it isn’t sure if Intel will continue to have a definite lead here as with HKMG and FinFET, once, although 10nm SuperFin’s SuperMIM shows that it will likely still remain one of Intel’s strengths in process technology going forward.

Investor Takeaway

All in all, when a company announces a new process, investors of TSMC and Intel should look out if they see any special claims about it besides the standard density or PPA (power-performance-area) improvements, such as FinFET at Intel 22nm. (This paragraph was written before, indeed, Intel announced 10nm SuperFin with exactly such a “special” claim.) Again: these could be changes not related to density, but also with important benefits. Or as TSMC’s 20nm shows: some aspects such as leakage might cause real headwinds if no innovations are introduced to improve those (which may or may not provide any clues about how good of a node TSMC’s 3N will be).

In that respect, the next major milestone for Intel will be at 7nm, as it has claimed a substantial 4x reduction in design rules, largely due to the introduction of EUV. The implication of this should be a much faster design + ramp of products, at least if the yield allows, but EUV should also help for yield [which apparently it will not].

Next (although admittedly “next” is a recurring theme since 14nm), and for Intel now even more important, given the 7nm issues, the divergence of Intel/TSMC at 5nm/N3 with regards to gate-all-around will be the next benchmark to see whose materials science and process innovation is really up to snuff.

TSMC staying with FinFET for 3N might or might not provide a clue of who will be leading. On the other hand, if the 7nm delay also impacts 5nm (which Intel has not provided any clarifications about yet), Intel and TSMC might enter the nanowire era around the same time. In any case, the common, overly doom-and-gloom picture concerning Intel’s process technology among investors, seems quite out of touch with reality and might need a serious calibration, as even Nvidia’s CEO suggested.

Disclosure: I/we have no positions in any stocks mentioned, and no plans to initiate any positions within the next 72 hours. I wrote this article myself, and it expresses my own opinions. I am not receiving compensation for it (other than from Seeking Alpha). I have no business relationship with any company whose stock is mentioned in this article.

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